Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
A General Proof for Overlapped Multiple-Bit Scanning Multiplications
IEEE Transactions on Computers
Hard-Wired Multipliers with Encoded Partial Products
IEEE Transactions on Computers
A 16-Bit x 16-Bit MAC Design Using Fast 5: 2 Compressors
ASAP '00 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
Circuit Design Techniques for a Gigahertz Integer Microprocessor
ICCD '98 Proceedings of the International Conference on Computer Design
A novel FPGA logic block for improved arithmetic performance
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Improving synthesis of compressor trees on FPGAs via integer linear programming
Proceedings of the conference on Design, automation and test in Europe
An FPGA Logic Cell and Carry Chain Configurable as a 6:2 or 7:2 Compressor
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Power efficient partial product compression
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
VHDL code generator for optimized carry-save reduction strategy in low power computer arithmetic
CSCC'11 Proceedings of the 2nd international conference on Circuits, Systems, Communications & Computers
Low power Wallace multiplier design based on wide counters
International Journal of Circuit Theory and Applications
International Journal of High Performance Systems Architecture
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3:2 counters and 4:2 compressors have been widely used for multiplier implementations. In this paper, a fast 5:3 compressor is derived for high-speed multiplier implementations. The fast 5:3 compression is obtained by applying two rows of fast 2-bit adder cells to five rows in a partial product matrix. As a design example, a 16-bit by 16-bit MAC (Multiply and Accumulate) design is investigated both in a purely logical gate implementation and in a highly customized design. For the partial product reduction, the use of the new 5:3 compression leads to 14.3% speed improvement in terms of XOR gate delay. In a dynamic CMOS circuit implementation using 0.225 μm bulk CMOS technology, 11.7% speed improvement is observed with 8.1% less power consumption for the reduction tree.