High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree
IEEE Transactions on Computers
Computer Arithmetic: Principles, Architecture and Design
Computer Arithmetic: Principles, Architecture and Design
Introduction to Arithmetic for Digital Systems Designers
Introduction to Arithmetic for Digital Systems Designers
Hard-Wired Multipliers with Encoded Partial Products
IEEE Transactions on Computers
CMOS floating-point unit for the S/390 parallel enterprise server G4
IBM Journal of Research and Development - Special issue: IBM S/390 G3 and G4
Comparison of Single- and Dual-Pass Multiply-Add Fused Floating-Point Units
IEEE Transactions on Computers
A 16-Bit by 16-Bit MAC Design Using Fast 5: 3 Compressor Cells
Journal of VLSI Signal Processing Systems
IEEE Transactions on Computers
Digit-Set Conversions: Generalizations and Applications
IEEE Transactions on Computers
Variable radix-2 multibit coding for 400 Mpixel/s DCT/IDCT of HDTV video decoder
Integration, the VLSI Journal
Minimal Weight Digit Set Conversions
IEEE Transactions on Computers
Parallel encrypted array multipliers
IBM Journal of Research and Development - Nanostructure technology
FPU Implementations with Denormalized Numbers
IEEE Transactions on Computers
The S/390 G5 floating-point unit
IBM Journal of Research and Development
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Because of recent advances in technology, multibit scanning implementations can be considered that exceed three-bit and four-bit groupings. The generalized proof for the multibit overlapped scanning multiplication is introduced, and the multiplication process is discussed. The proofs are intended to establish the correctness of the decode and the actions taken to produce the multiplication of any valid scheme proposed in the past, and to dictate the correct decode and actions taken for any overlapped s-bit scanning algorithm such that s is a natural number greater than or equal to two. The multiplication is considered to be between two fractional numbers, which are represented in two's-complement form