A General Proof for Overlapped Multiple-Bit Scanning Multiplications
IEEE Transactions on Computers
Computer Arithmetic: Principles, Architecture and Design
Computer Arithmetic: Principles, Architecture and Design
Introduction to Arithmetic for Digital Systems Designers
Introduction to Arithmetic for Digital Systems Designers
Hard-Wired Multipliers with Encoded Partial Products
IEEE Transactions on Computers
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An algorithm for direct two's-complement and sign-magnitude parallel multiplication is described. The partial product matrix representing the multiplication is converted to an equivalent matrix by encryption. Its reduction, producing the final result, needs no specialized adders and can be added with any parallel array addition technique. It contains no negative terms and no extra "correction" rows; in addition, it produces the multiplication with fewer than the minimal number of rows required for a direct multiplication process.