Review: New redundant logic design concept for high noise and low voltage scenarios

Authors:
Lancelot García-Leyva;Dennis Andrade;Sergio Gómez;Antonio Calomarde;Francesc Moll;Antonio Rubio
Affiliations:
Universidad Autónoma de Tlaxcala, FCBIyT, C/Apizaquito s/n, Apizaco, 90300 Tlaxcala, Mexico and Universitat Politènica de Catalunya, Department of Electronic Engineering, C/Jordi Girona ...;Universitat Politènica de Catalunya, Department of Electronic Engineering, C/Jordi Girona 31, 08034 Barcelona, Spain;Universitat Politènica de Catalunya, Department of Electronic Engineering, C/Jordi Girona 31, 08034 Barcelona, Spain;Universitat Politènica de Catalunya, Department of Electronic Engineering, C/Jordi Girona 31, 08034 Barcelona, Spain;Universitat Politènica de Catalunya, Department of Electronic Engineering, C/Jordi Girona 31, 08034 Barcelona, Spain;Universitat Politènica de Catalunya, Department of Electronic Engineering, C/Jordi Girona 31, 08034 Barcelona, Spain
Venue:
Microelectronics Journal
Year:
2011

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Abstract

This paper presents a new redundant logic design concept named Turtle Logic (TL). It is a new probabilistic logic method based on port redundancy and complementary data, oriented toward emerging technologies beyond CMOS, where the thermal noise could be predominant and the reliability of the future circuits could be limited. The TL is a technology independent method, which aims to improve error tolerance when these errors are caused by noise within logic and functional units, sequential elements, and in general synchronous pipeline Finite State Machines. Turtle Logic operation is based on the consistency relation of redundant inputs. In the case of discrepancy, the output of the system keeps the previous value, therefore avoiding the propagation of incorrect inputs. A two's complement 8x8-bit pipelined Baugh-Wooley multiplier is implemented, on which several experiments reveal a perfect tolerance (0% errors) to single line discrepancies for both primary and internal nodes, with a cost of lost clock periods between 6% and 25%. The error ratio for the proposed Turtle Logic implementation with double discrepancies in both true and complementary lines are lower than 0.1% when the noise affects primary input nodes, and lower than 0.9% when the noise affects internal nodes.