Review: New redundant logic design concept for high noise and low voltage scenarios
Microelectronics Journal
Proceedings of the International Conference on Computer-Aided Design
Comparing the performance of stochastic simulation on GPUs and OpenMP
International Journal of Computational Science and Engineering
Survey of Stochastic Computing
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on Probabilistic Embedded Computing
Stochastic circuits for real-time image-processing applications
Proceedings of the 50th Annual Design Automation Conference
Energy-efficient multiplier-less discrete convolver through probabilistic domain transformation
Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays
Sequential logic to transform probabilities
Proceedings of the International Conference on Computer-Aided Design
| Hi-index | 14.98 |
Mounting concerns over variability, defects, and noise motivate a new approach for digital circuitry: stochastic logic, that is to say, logic that operates on probabilistic signals and so can cope with errors and uncertainty. Techniques for probabilistic analysis of circuits and systems are well established. We advocate a strategy for synthesis. In prior work, we described a methodology for synthesizing stochastic logic, that is to say logic that operates on probabilistic bit streams. In this paper, we apply the concept of stochastic logic to a reconfigurable architecture that implements processing operations on a datapath. We analyze cost as well as the sources of error: approximation, quantization, and random fluctuations. We study the effectiveness of the architecture on a collection of benchmarks for image processing. The stochastic architecture requires less area than conventional hardware implementations. Moreover, it is much more tolerant of soft errors (bit flips) than these deterministic implementations. This fault tolerance scales gracefully to very large numbers of errors.