On the expressibility of stochastic switching circuits
ISIT'09 Proceedings of the 2009 IEEE international conference on Symposium on Information Theory - Volume 3
The robustness of stochastic switching networks
ISIT'09 Proceedings of the 2009 IEEE international conference on Symposium on Information Theory - Volume 3
An Architecture for Fault-Tolerant Computation with Stochastic Logic
IEEE Transactions on Computers
| Hi-index | 0.00 |
Energy efficiency and algorithmic robustness typically are conflicting circuit characteristics, yet with CMOS technology scaling towards 10-nm feature size, both become critical design metrics simultaneously for modern logic circuits. This paper propose a novel computing scheme hinged on probabilistic domain transformation aiming for both low power operation and fault resilience. In such a computing paradigm, algorithm inputs are first encoded through probabilistic means, which translates the input values into a number of random samples. Subsequently, light-weight operations, such as sim- ple additions will be performed onto these random samples in order to generate new random variables. Finally, the resulting random samples will be decoded probabilistically to give the final results.