An Accurate SER Estimation Method Based on Propagation Probability
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Technology Mapping for Reliability Enhancement in Logic Synthesis
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Soft delay error analysis in logic circuits
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Soft error modeling and remediation techniques in ASIC designs
Microelectronics Journal
Review: New redundant logic design concept for high noise and low voltage scenarios
Microelectronics Journal
Coupling induced soft error mechanisms in nanoscale CMOS technologies
Analog Integrated Circuits and Signal Processing
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Transient faults in VLSI circuits could lead to disastrous consequences. With technology scaling, circuits are becoming increasingly vulnerable to transient faults. This paper presents an accurate and efficient method to estimate fault-sensitivity of VLSI circuits. Using a binary counter and an RC5 encryption implementation as examples, this paper shows that by performing a limited amount of random simulations, fault sensitivity can be estimated accurately at a reasonably low computational cost. This method is then used to show that the combination of two circuit level techniques can make circuits more fault-tolerant than using these techniques individually.