Fixed-width multipliers for the implementation of efficient digital FIR filters

Authors:
Valeria Garofalo
Affiliations:
Department of Electronic Engineering and Telecommunication, University of Naples "Federico II", via Claudio 21, I-80125 Naples, Italy
Venue:
Microelectronics Journal
Year:
2008

Citing 1
Cited 1

A Two's Complement Parallel Array Multiplication Algorithm

IEEE Transactions on Computers

FPGA realization of FIR filters for high-speed and medium-speed by using modified distributed arithmetic architectures

Microelectronics Journal

Quantified Score

Hi-index	0.00

Visualization

Abstract

The use of fixed-width multiplier for the implementation of FIR filters is investigated in this paper. The paper presents a review of the existing fixed-width multiplier architectures and analytically calculates the error introduced by the use of fixed-width multipliers in the realization of FIR filters. FIR filters are implemented in TSMC 0.18@mm technology using state-of-the-art fixed-width multipliers, varying the architecture and the width of the output. The analysis shows that fixed-width multipliers are a suitable replacement for the full-width multiplier. Furthermore the best trade-off between error, silicon area occupation and power is provided by the LMS fixed-width multiplier. As example a FIR filter with 16b fixed-width multiplier provides a reduction of 16% in area and 18% in power dissipation with a 22% increase of the working frequency, while keeping the mean square error below 14LSB^2.