Fast MPEG-4 Motion Estimation: Processor Based and Flexible VLSI Implementations
Journal of VLSI Signal Processing Systems - Special issue on implementation of MPEG-4 multimedia codecs
Parallel Saturating Fractional Arithmetic Units
GLS '99 Proceedings of the Ninth Great Lakes Symposium on VLSI
The Sum-Absolute-Difference Motion Estimation Accelerator
EUROMICRO '98 Proceedings of the 24th Conference on EUROMICRO - Volume 2
The MOLEN Polymorphic Processor
IEEE Transactions on Computers
Reconfigurable universal SAD-multiplier array
Proceedings of the 2nd conference on Computing frontiers
A Two's Complement Parallel Array Multiplication Algorithm
IEEE Transactions on Computers
High-bandwidth Address Generation Unit
Journal of Signal Processing Systems
High-bandwidth address generation unit
SAMOS'07 Proceedings of the 7th international conference on Embedded computer systems: architectures, modeling, and simulation
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In this paper, we investigate the collapsing of eight multi-operand addition related operations into a single and common (3:2) counter array. We consider for this unit multiplication in integer and fractional representations, the Sum of Absolute Differences (SAD) in unsigned, signed magnitude and two's complement notation. Furthermore, the unit also incorporates a Multiply-Accumulation unit (MAC) for two's complement notation. The proposed multiple operation unit was constructed around 10 element arrays that can be reduced using well known counter techniques, which are feed with the necessary data to perform the proposed eight operations. It is estimated that 6/8 of the basic (3:2) counter array is shared by the operations. The obtained results of the presented unit indicates that is capable of processing a 4x4 SAD macro-block in 36.35 ns and takes 30.43 ns to process the rest of the operations using a VIRTEX II PRO xc2vp100-7ff1696 FPGA device.