Fast MPEG-4 Motion Estimation: Processor Based and Flexible VLSI Implementations
Journal of VLSI Signal Processing Systems - Special issue on implementation of MPEG-4 multimedia codecs
Reconfigurable computing: a survey of systems and software
ACM Computing Surveys (CSUR)
Internet Streaming SIMD Extensions
Computer
VIS Speeds New Media Processing
IEEE Micro
The Sum-Absolute-Difference Motion Estimation Accelerator
EUROMICRO '98 Proceedings of the 24th Conference on EUROMICRO - Volume 2
The MOLEN Polymorphic Processor
IEEE Transactions on Computers
Reconfigurable multiple operation array
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
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In this paper, we investigate the collapsing of some multi-operand addition related operations into a single array. More specifically we consider multiplication and Sum of Absolute Differences (SAD) and propose an array capable of performing the aforementioned operations for unsigned, signed magnitude, and two's complement notations. The array, called a universal array, is divided into common and controlled logic blocks intended to be reconfigured dynamically. The proposed unit was constructed around three main operational fields, which are feed with the necessary data products or SAD addition terms in order to compute the desired operation. It is estimated that a 66.6% of the (3:2)counter array is shared by the operations providing an opportunity to reduce reconfiguration times. The synthesis result for a FPGA device, of the new structure, was compared against other multiplier organizations. The obtained results indicate that the proposed unit is capable of processing in 23.9 ns a 16 bit multiplication, and that an 8 input SAD can be computed in 29.8 ns using current FPGA technology. Even though the proposed structure incorporates more operations, the extra delay required over conventional structures is very small in the order of 1% compared to Baugh&Wooley multiplier