VLSI array processors
Discrete cosine transform: algorithms, advantages, applications
Discrete cosine transform: algorithms, advantages, applications
Digital video processing
Motion Estimation Algorithms for Video Compression
Motion Estimation Algorithms for Video Compression
Image and Video Compression Standards: Algorithms and Architectures
Image and Video Compression Standards: Algorithms and Architectures
Algorithms, Complexity Analysis and VLSI Architectures for MPEG-4 Motion Estimation
Algorithms, Complexity Analysis and VLSI Architectures for MPEG-4 Motion Estimation
Design Trade-Offs for Real-Time Block Matching Motion Estimation Algorithms
ACCV '95 Invited Session Papers from the Second Asian Conference on Computer Vision: Recent Developments in Computer Vision
ICASSP '97 Proceedings of the 1997 IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP '97) -Volume 4 - Volume 4
Computationally efficient exhaustive search algorithm for rate-constrained motion estimation
ICIP '97 Proceedings of the 1997 International Conference on Image Processing (ICIP '97) 3-Volume Set-Volume 1 - Volume 1
A new prediction model search algorithm for fast block motion estimation
ICIP '97 Proceedings of the 1997 International Conference on Image Processing (ICIP '97) 3-Volume Set-Volume 3 - Volume 3
A new stochastic block matching algorithm (SBMA) for video coding based on modified 3-step search
ICASSP '96 Proceedings of the Acoustics, Speech, and Signal Processing, 1996. on Conference Proceedings., 1996 IEEE International Conference - Volume 04
An efficient motion estimation technique based on a rate-distortion criterion
ICASSP '96 Proceedings of the Acoustics, Speech, and Signal Processing, 1996. on Conference Proceedings., 1996 IEEE International Conference - Volume 04
A binary block matching architecture with reduced power consumption and silicon area requirement
ICASSP '96 Proceedings of the Acoustics, Speech, and Signal Processing, 1996. on Conference Proceedings., 1996 IEEE International Conference - Volume 06
A cost effective motion estimation processor LSI using a simple and efficient algorithm
IEEE Transactions on Consumer Electronics
Predictive RD optimized motion estimation for very low bit-rate video coding
IEEE Journal on Selected Areas in Communications
VLSI architectures for block matching algorithms using systolic arrays
IEEE Transactions on Circuits and Systems for Video Technology
A flexible parallel architecture adapted to block-matching motion-estimation algorithms
IEEE Transactions on Circuits and Systems for Video Technology
A novel four-step search algorithm for fast block motion estimation
IEEE Transactions on Circuits and Systems for Video Technology
Efficient block motion estimation using integral projections
IEEE Transactions on Circuits and Systems for Video Technology
Low-complexity block-based motion estimation via one-bit transforms
IEEE Transactions on Circuits and Systems for Video Technology
A comparison of block-matching algorithms mapped to systolic-array implementation
IEEE Transactions on Circuits and Systems for Video Technology
A high performance fast search algorithm for block matching motion estimation
IEEE Transactions on Circuits and Systems for Video Technology
A methodology to evaluate memory architecture design tradeoffs for video signal processors
IEEE Transactions on Circuits and Systems for Video Technology
A new block-matching criterion for motion estimation and its implementation
IEEE Transactions on Circuits and Systems for Video Technology
A fast hierarchical motion vector estimation algorithm using mean pyramid
IEEE Transactions on Circuits and Systems for Video Technology
VLSI architecture for a flexible block matching processor
IEEE Transactions on Circuits and Systems for Video Technology
Reconfigurable universal SAD-multiplier array
Proceedings of the 2nd conference on Computing frontiers
Scalable high-throughput variable block size motion estimation architecture
Microprocessors & Microsystems
ICC'08 Proceedings of the 12th WSEAS international conference on Circuits
Reduced-bit, full search block-matching algorithms and their hardware realizations
ACIVS'05 Proceedings of the 7th international conference on Advanced Concepts for Intelligent Vision Systems
Reconfigurable architecture for VBSME with variable pixel precision
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Reconfigurable multiple operation array
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
Bit-by-Bit Pipelined and Hybrid-Grained 2D Architecture for Motion Estimation of H.264/AVC
Journal of Signal Processing Systems
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MPEG-4 is a new multimedia standard combining interactivity,object-based natural and synthetic digital video, audio andcomputer-graphics. For the implementation of the video part of theMPEG-4 standard a high degree of flexibility is required, where themotion estimation requires the highest part of the computationalpower. Therefore, in this paper fast algorithms for MPEG-4 motionestimation are evaluated in terms of visual quality and computationalpower requirements for processor based implementations. Due to theobject-based nature of MPEG-4 also new VLSI architectures for MPEG-4motion estimation are required. Therefore known motion estimationarchitectures are evaluated on their capability of being modified forMPEG-4 support. Based on this evaluation a new dedicated, butflexible MPEG-4 motion estimation architecture targeted for low-powerhandheld applications is presented, which resulted to be advantageousto processor based implementations by magnitudes of order.