Scalable high-throughput variable block size motion estimation architecture

Authors:
Stephen Warrington;Wai-Yip Chan;Subramania Sudharsanan
Affiliations:
Magnum Semiconductor, Inc., Waterloo, ON, N2V 1C5, Canada;Department of Electrical and Computer Engineering, Queen's University, Kingston, ON, K7L 3N6, Canada;Digeo, Inc., Kirkland, WA 98033, USA
Venue:
Microprocessors & Microsystems
Year:
2009

Citing 6
Cited 0

Fast MPEG-4 Motion Estimation: Processor Based and Flexible VLSI Implementations

Journal of VLSI Signal Processing Systems - Special issue on implementation of MPEG-4 multimedia codecs
A fast VLSI architecture for full-search variable block size motion estimation in MPEG-4 AVC/H.264

Proceedings of the 2005 Asia and South Pacific Design Automation Conference
A fast three-step search algorithm with minimum checking points using unimodal error surface assumption

IEEE Transactions on Consumer Electronics
Overview of the H.264/AVC video coding standard

IEEE Transactions on Circuits and Systems for Video Technology
Analysis and complexity reduction of multiple reference frames motion estimation in H.264/AVC

IEEE Transactions on Circuits and Systems for Video Technology
VLSI architecture for a flexible block matching processor

IEEE Transactions on Circuits and Systems for Video Technology

Quantified Score

Hi-index	0.01

Visualization

Abstract

Variable block size (VBS) motion compensated prediction (MCP) provides substantial rate-distortion performance gain over conventional fixed-block-size MCP and is a key feature of the H.264/AVC video coding standard. VBS-MCP requires the encoder to perform VBS motion estimation (VBSME), a computationally complex operation. In this paper, we propose a high motion vector throughput full-search VBSME architecture. High performance is achieved by performing parallel computations for multiple pixels within a macroblock, as well as computing several candidate motion vector (MV) positions in parallel. Two implementations of the architecture are examined, a four pixel-parallel implementation, and a higher performance 16 pixel-parallel implementation. A high degree of scalability is achieved by allowing for a variable length processing element array, where more processing elements yields a higher degree of candidate MV parallelism. The proposed architecture achieves a throughput exceeding current full-search VBSME architectures.