Fast MPEG-4 Motion Estimation: Processor Based and Flexible VLSI Implementations
Journal of VLSI Signal Processing Systems - Special issue on implementation of MPEG-4 multimedia codecs
Data memory design and exploration for low-power embedded systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Memory Design and Exploration for Low Power, Embedded Systems
Journal of VLSI Signal Processing Systems - Special issue on signal processing systems design and implementation
Configurable parallel memory architecture for multimedia computers
Journal of Systems Architecture: the EUROMICRO Journal
Scalable Architecture for SoC Video Encoders
Journal of VLSI Signal Processing Systems
Memory power optimization of hardware implementations of multimedia applications onto FPGA platforms
Journal of Embedded Computing - Low-power Embedded Systems
Design of an H.264/AVC Decoder with Memory Hierarchy and Line-Pixel-Lookahead
Journal of Signal Processing Systems
Configurable data memory for multimedia processing
Journal of Signal Processing Systems - Special Issue: Embedded computing systems for DSP
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Develops a methodology for the design of the memory and the memory-processor communication network in video signal processors. The memory subsystem is the bottleneck of most video computing systems and its design requires evaluating tradeoffs between area, cycle time, and utilization. We emphasize the need to consider technological and circuit-level issues during the design of a system architecture, particularly video signal processing (VSP) systems, and present a systematic method whereby the organization of the memory architecture can be analyzed and its cycle-time approximated before a detailed design is undertaken. We show how variations in sizes and circuit configurations help determine the variations in delay of both memory and network, and how the delay curves, thus determined, can be used to design, compare, and choose from different memory-system architectures; we also describe a technique that can be used to identify the on-chip-off-chip boundary with respect to a hierarchical memory-system design for a memory-intensive VSP module. All of our results are validated via layout and simulation of prototype circuits in two different process technologies. Motion estimation and discrete cosine transform (DCT) being two of the most important tasks in video processing, we use the design of a motion estimator and that of a DCT unit as examples to illustrate the high-level issues in designing the memory architecture for a VSP module. The analysis presented for the motion estimator and the DCT unit can also be applied to other processing blocks belonging to the system