Memory power optimization of hardware implementations of multimedia applications onto FPGA platforms

Authors:
K. Tatas;D. Soudris;A. Thanailakis
Affiliations:
VLSI Design and Testing Center, Department of Electrical and Computer Engineering, Democritus University of Thrace, Xanthi, 67100, Greece (Correspoding author. E-mail: ktatas@ee.duth.gr);VLSI Design and Testing Center, Department of Electrical and Computer Engineering, Democritus University of Thrace, Xanthi, 67100, Greece;VLSI Design and Testing Center, Department of Electrical and Computer Engineering, Democritus University of Thrace, Xanthi, 67100, Greece
Venue:
Journal of Embedded Computing - Low-power Embedded Systems
Year:
2005

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Abstract

An optimization methodology that combines high-level exploration with Register Transfer Level (RTL) design for the power-efficient estimation of motion estimation algorithms on a system comprised by an FPGA and an external memory is presented. Low power consumption is achieved by implementing an optimum on-chip memory hierarchy inside the FPGA, and moving the bulk of required memory transfers from the internal memory hierarchy instead of the external memory. A case study of three popular multimedia kernels is performed for a number of different FPGA devices. Comparisons among implementations with and without this optimization, prove that great power efficiency can be achieved while satisfying performance constraints.