The Impact of Rate Control Algorithms on System-Level VLSI Design
Journal of VLSI Signal Processing Systems
Maximizing memory data reuse for lower power motion estimation
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
Fast MPEG-4 Motion Estimation: Processor Based and Flexible VLSI Implementations
Journal of VLSI Signal Processing Systems - Special issue on implementation of MPEG-4 multimedia codecs
FPGA implementation of a novel, fast motion estimation algorithm for real-time video compression
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
A Parallel Accelerator Architecture for Multimedia Video Compression
Euro-Par '99 Proceedings of the 5th International Euro-Par Conference on Parallel Processing
Hierarchical Block Matching Motion Estimation on a Hypercube Multiprocessor
ParNum '99 Proceedings of the 4th International ACPC Conference Including Special Tracks on Parallel Numerics and Parallel Computing in Image Processing, Video Processing, and Multimedia: Parallel Computation
Granularity Levels in Parallel Block-Matching Motion Compensation
Proceedings of the 9th European PVM/MPI Users' Group Meeting on Recent Advances in Parallel Virtual Machine and Message Passing Interface
Real-Time Imaging - Special issue on software engineering
High Performance Array Processor for Video Decoding
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Survey on Block Matching Motion Estimation Algorithms and Architectures with New Results
Journal of VLSI Signal Processing Systems
Energy-efficient acceleration of MPEG-4 compression tools
EURASIP Journal on Embedded Systems
Fast motion estimation using configurable and extendible processing cores
Asilomar'09 Proceedings of the 43rd Asilomar conference on Signals, systems and computers
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This paper presents an evaluation of several well-known block-matching motion estimation algorithms from a system-level very large scale integration (VLSI) design viewpoint. Because a straightforward block-matching algorithm (BMA) demands a very large amount of computing power, many fast algorithms have been developed. However, these fast algorithms are often designed to merely reduce arithmetic operations without considering their overall performance in VLSI implementation. Three criteria are used to compare various block-matching algorithms: (1) silicon area, (2) input/output requirement, and (3) image quality. A basic systolic array architecture is chosen to implement all the selected algorithms. The purpose of this study is to compare these representative BMAs using the aforementioned criteria. The advantages/disadvantages of these algorithms in terms of their hardware tradeoff are discussed. The methodology and results presented provide useful guidelines to system designers in selecting a BMA for VLSI implementation