FPGA implementation of a novel, fast motion estimation algorithm for real-time video compression

Authors:
S. Ramachandran;S. Srinivasan
Affiliations:
Department of Electrical Engineering, Indian Institute of Technology, Madras, Chennai-600 036, India;Department of Electrical Engineering, Indian Institute of Technology, Madras, Chennai-600 036, India
Venue:
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
Year:
2001

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Abstract

A novel block matching algorithm for motion estimation in a video frame sequence, well suited for a high performance FPGA implementation is presented in this paper. The algorithm is up to 40% faster when compared to one of the fastest existing algorithms, viz., one-at-a-time step search algorithm without compromising either in the image quality or in the compression effected. The speed advantage is preserved even in the event of a sudden scene change in a video sequence. The proposed algorithm is also capable of dynamically detecting the direction of motion of image blocks. The FPGA implementation of the algorithm is capable of processing color pictures of sizes up to 1024x768 pixels at the real time video rate of 25 frames/second and conforms to MPEG-2 standards.