Hardware implementation of a disparity estimation scheme for real-time compression in 3D imaging applications

Authors:
D. Chaikalis;N. Sgouros;D. Maroulis;P. Papageorgas
Affiliations:
National and Kapodistrian University of Athens, Department of Informatics and Telecommunications, Panepistimiopolis, Ilisia, Athens 15784, Greece;National and Kapodistrian University of Athens, Department of Informatics and Telecommunications, Panepistimiopolis, Ilisia, Athens 15784, Greece;National and Kapodistrian University of Athens, Department of Informatics and Telecommunications, Panepistimiopolis, Ilisia, Athens 15784, Greece;Technological Educational Institute of Piraeus, Department of Electronics, Petrou Ralli & Thivon Avenue, Egaleo, Athens 12244, Greece
Venue:
Journal of Visual Communication and Image Representation
Year:
2008

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Abstract

This paper presents a novel hardware implementation of a disparity estimation scheme targeted to real-time Integral Photography (IP) image and video sequence compression. The software developed for IP image compression achieves high quality ratios over classic methodologies by exploiting the inherent redundancy that is present in IP images. However, there are certain time constraints to the software approach that must be confronted in order to address real-time applications. Our main effort is to achieve real-time performance by implementing in hardware the most time-consuming parts of the compression algorithm. The proposed novel digital architecture features minimized memory read operations and extensive simultaneous processing, while taking into concern the memory and data bandwidth limitations of a single FPGA implementation. Our results demonstrate that the implemented hardware system can successfully process high resolution IP video sequences in real-time, addressing a vast range of applications, from mobile systems to demanding desktop displays.