The instruction systolic array, a parallel architecture for VLSI
Integration, the VLSI Journal
HPCN Europe 1994 Proceedings of the nternational Conference and Exhibition on High-Performance Computing and Networking Volume II: Networking and Tools
Euro-Par '98 Proceedings of the 4th International Euro-Par Conference on Parallel Processing
A comparison of block-matching algorithms mapped to systolic-array implementation
IEEE Transactions on Circuits and Systems for Video Technology
VLSI implementations of image and video multimedia processing systems
IEEE Transactions on Circuits and Systems for Video Technology
New systolic array implementation of the 2-D discrete cosine transform and its inverse
IEEE Transactions on Circuits and Systems for Video Technology
A hybrid architecture for bioinformatics
Future Generation Computer Systems - Parallel computing technologies (PaCT-2001)
Massively Parallel Solutions for Molecular Sequence Analysis
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
Protein Sequence Comparison on the Instruction Systolic Array
PaCT '01 Proceedings of the 6th International Conference on Parallel Computing Technologies
Scanning Biosequence Databases on a Hybrid Parallel Architecture
Euro-Par '01 Proceedings of the 7th International Euro-Par Conference Manchester on Parallel Processing
Design of a Parallel Accelerator for Volume Rendering
Euro-Par '00 Proceedings from the 6th International Euro-Par Conference on Parallel Processing
An area-efficient bit-serial integer and GF(2n) multiplier
Microelectronic Engineering
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This paper describes a parallel architecture for a variety of algorithms for video compression. It has been designed to meet the requirements of encoding and decoding according to the ITU-T standard H.263. The architecture is an implementation of the instruction systolic array (ISA) model which combines the simplicity of systolic arrays with the flexibility of a programmable parallel computer. Although the parallel accelerator unit is implemented on no more than 9 mm2 of silicon it suffices to meet the compression rate necessary to send a compressed video stream through a standard ISDN terminal interface.