High-bandwidth address generation unit

Authors:
Humberto Calderón;Carlo Galuzzi;Georgi Gaydadjiev;Stamatis Vassiliadis
Affiliations:
Computer Engineering Laboratory, Electrical Engineering Dept., EEMCS, TU Delft, The Netherlands;Computer Engineering Laboratory, Electrical Engineering Dept., EEMCS, TU Delft, The Netherlands;Computer Engineering Laboratory, Electrical Engineering Dept., EEMCS, TU Delft, The Netherlands;Computer Engineering Laboratory, Electrical Engineering Dept., EEMCS, TU Delft, The Netherlands
Venue:
SAMOS'07 Proceedings of the 7th international conference on Embedded computer systems: architectures, modeling, and simulation
Year:
2007

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Abstract

In this paper we describe an efficient data fetch circuitry for retrieving several operands from a n-bank interleaved memory system in a single machine cycle. The proposed address generation (AGEN) unit operates with a modified version of the low-order-interleaved memory access approach. Our design supports data structures with arbitrary lengths and different (odd) strides. A detailed discussion of the 32-bit AGEN design aimed at multiple-operand functional units is presented. The experimental results indicate that our AGEN is capable of producing 8 × 32-bit addresses every 6 ns for different stride cases when implemented on VIRTEX-II PRO xc2vp30-7ff1696 FPGA device using trivial hardware resources.