Interleaved Parallel Schemes

Authors:
André Seznec;Jacques Lenfant
Affiliations:
-;-
Venue:
IEEE Transactions on Parallel and Distributed Systems
Year:
1994

Citing 1
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Abstract

On vector supercomputers, vector register processors share a global highly interleavedmemory. In order to optimize memory throughput, a single-instruction, multiple-data(SIMD) synchronization mode may be used on vector sections. We present an interleavedparallel scheme (IPS). Using IPS ensures an equitable distribution of elements on a highly interleaved memory for a wide range of vector strides. Access to memory may beorganized in such a way that conflicts are avoided on memory and on the interconnectionnetwork.