IEEE Transactions on Parallel and Distributed Systems
Implementation of a UMTS Turbo-Decoder on a Dynamically Reconfigurable Platform
Proceedings of the conference on Design, automation and test in Europe - Volume 2
A design approach dedicated to network-based and conflict-free parallel interleavers
Proceedings of the great lakes symposium on VLSI
Mapping interleaving laws to parallel turbo and LDPC decoder architectures
IEEE Transactions on Information Theory
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Recent communication standards and storage systems uses parallel architectures for error correcting codes (LDPC or Turbo-codes) to reliably transfer data between two equipments. However, parallel architectures suffer from memory access conflicts. In this paper, we present a method that finds a conflict-free memory mapping for any interleaving law and any parallelism. The proposed approach always complies with the interconnection network topology the designer wants to infer. Moreover, the resulting architecture is optimized by reducing the cost of network and controller (network and memory controller) architectures.