Reconfigurable Fixed Point Dense and Sparse Matrix-Vector Multiply/Add Unit

  • Authors:

  • Humberto Calderon;Stamatis Vassiliadis

  • Affiliations:

  • Electrical Engineering Dept.,EEMCS,TU Delft, The Netherlands;Electrical Engineering Dept.,EEMCS,TU Delft, The Netherlands

  • Venue:
  • ASAP '06 Proceedings of the IEEE 17th International Conference on Application-specific Systems, Architectures and Processors
  • Year:
  • 2006

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Abstract

In this paper, we propose a reconfigurable hardware accelerator for fixed-point-matrix-vector-multiply/add operations, capable to work on dense and sparse matrices formats. The prototyped hardware unit accommodates 4 dense or sparse matrix inputs and performs computations in a space parallel design achieving 4 multiplications and up to 12 additions at 120 MHz over an xc2vp100-6 FPGA device, reaching a throughput of 1.9 GOPS. A total of 11 units can be integrated in the same FPGA chip, achieving a performance of 21 GOPS.