Quality-driven model-based architecture synthesis for real-time embedded SoCs
Journal of Systems Architecture: the EUROMICRO Journal
Modern development methods and tools for embedded reconfigurable systems: A survey
Integration, the VLSI Journal
High-bandwidth address generation unit
SAMOS'07 Proceedings of the 7th international conference on Embedded computer systems: architectures, modeling, and simulation
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This paper deals with methods of automated memory synthesis for Custom Computing Machines (CCMs). We focus the presentation on the synthesis of interleaved memory systems, which provide the quickest access to data at the cost of more parallel hardware.The synthesis of an interleaved memory system starts with the analysis of data access patterns in the algorithm, from which a number of possible storage schemes is derived. The storage scheme defines how the array elements can be distributed among different memory banks. The best storage scheme is then chosen according to a complex metric of cost and performance of the required memory system. This metric involves the schedule length of operations, the type and number of required memory chips, the cost and delay of address generation and the interconnection network.Results of our experiments demonstrate that the developed methods are capable to automatically synthesise storage schemes and interleaved memory systems, which are the same or better than those previously conceived by an experienced hardware designer.