Parallel Saturating Fractional Arithmetic Units

Authors:
Navindra Yadav;Michael Schulte;John Glossner
Affiliations:
-;-;-
Venue:
GLS '99 Proceedings of the Ninth Great Lakes Symposium on VLSI
Year:
1999

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Abstract

This paper describes the designs of a saturating adder, multiplier, single MAC unit, and dual MAC unit with one cycle latencies. The dual MAC unit can perform two saturating MAC operations in parallel and accumulate the results with saturation. Specialized saturation logic ensures that the output of the dual MAC unit is identical to the result of the operations performed serially with saturation after each multiplication and each addition