Integer Multiplication with Overflow Detection or Saturation

Authors:
Michael J. Schulte;Pablo I. Balzola;Ahmet Akkas;Robert W. Brocato
Affiliations:
Lehigh Univ., Bethlehem, PA;Lehigh Univ., Bethlehem, PA;Lehigh Univ., Bethlehem, PA;Sandia National Labs, Albuquerque, NM
Venue:
IEEE Transactions on Computers - Special issue on computer arithmetic
Year:
2000

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Abstract

High-speed multiplication is frequently used in general-purpose and application-specific computer systems. These systems often support integer multiplication, where two $n$-bit integers are multiplied to produce a $2n$-bit product. To prevent growth in word length, processors typically return the $n$ least significant bits of the product and a flag that indicates whether or not overflow has occurred. Alternatively, some processors saturate results that overflow to the most positive or most negative representable number. This paper presents efficient methods for performing unsigned or two's complement integer multiplication with overflow detection or saturation. These methods have significantly less area and delay than conventional methods for integer multiplication with overflow detection or saturation.