Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
Integer Multiplication with Overflow Detection or Saturation
IEEE Transactions on Computers - Special issue on computer arithmetic
DSP Processor Fundamentals: Architectures and Features
DSP Processor Fundamentals: Architectures and Features
Integer multiplier and squarer architectures with overflow detection
Integer multiplier and squarer architectures with overflow detection
Integer squarers with overflow detection
Computers and Electrical Engineering
Enhanced-functionality multipliers
Journal of Systems Architecture: the EUROMICRO Journal
Evaluation of Sticky-Bit Generation Methods for Floating-Point Multipliers
Journal of Signal Processing Systems
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This paper presents a general approach for designing array and tree integer multipliers with overflow detection. The overflow detection techniques are based on an analysis of the magnitudes of the input operands. The overflow detection circuits operate in parallel with a simplified multiplier to reduce the overall area and delay.