Fast multiplication: algorithms and implementation
Fast multiplication: algorithms and implementation
167 MHz Radix-4 Floating Point Multiplier
ARITH '95 Proceedings of the 12th Symposium on Computer Arithmetic
Integer Multipliers with Overflow Detection
IEEE Transactions on Computers
A Regular Layout for Parallel Adders
IEEE Transactions on Computers
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IEEE-754 rounding support increases the critical delay for floating-point multipliers. Except round-to-zero mode all IEEE rounding modes test the (n − 2) least significant product bits for one. The result of the test is indicated by the sticky-bit. Since fast generation of the sticky-bit is critical for performance, various sticky-bit generation designs are developed. This paper presents a comparison of previous fast sticky-bit generation designs and proposes a novel design that is independent from the multiplier’s hardware. Thus, the proposed design can be used in any floating-point multiplier or any floating-point multiply-accumulate circuit. The proposed method is one of the fastest among all methods and it uses the minimum hardware resources among the designs that use the same idea.