A Comparison of Three Rounding Algorithms for IEEE Floating-Point Multiplication
IEEE Transactions on Computers - Special issue on computer arithmetic
Energy Efficient Adiabatic Multiplier-Accumulator Design
Journal of VLSI Signal Processing Systems
Integration, the VLSI Journal
Array-of-arrays architecture for parallel floating point multiplication
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
A New Divide and Conquer Method for Achieving High Speed Division in Hardware
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Modified booth truncated multipliers
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Secondary Radix Recodings for Higher Radix Multipliers
IEEE Transactions on Computers
Architecture and Implementation of a Vector/SIMD Multiply-Accumulate Unit
IEEE Transactions on Computers
A parametric error analysis of Goldschmidt's division algorithm
Journal of Computer and System Sciences
A novel configurable motion estimation architecture for high-efficiency MPEG-4/H.264 encoding
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Real-Time Systems
Fast hardware for modular exponentiation with efficient exponent pre-processing
Journal of Systems Architecture: the EUROMICRO Journal
Negative Save Sign Extension for Multi-term Adders and Multipliers
Journal of Signal Processing Systems
Partial product reduction by using look-up tables for M×N multiplier
Integration, the VLSI Journal
Evaluation of Sticky-Bit Generation Methods for Floating-Point Multipliers
Journal of Signal Processing Systems
A fully redundant decimal adder and its application in parallel decimal multipliers
Microelectronics Journal
A new redundant binary booth encoding for fast 2n-bit multiplier design
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Improving multiplication and reminder using implementation based on word and index
Proceedings of the 1st Amrita ACM-W Celebration on Women in Computing in India
The algorithm and circuit design of a 400MHz 16-bit hybrid multiplier
ACSAC'06 Proceedings of the 11th Asia-Pacific conference on Advances in Computer Systems Architecture
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