The design and analysis of VLSI circuits
The design and analysis of VLSI circuits
High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree
IEEE Transactions on Computers
The complexity of Boolean functions
The complexity of Boolean functions
A closer look at VLSI multiplication
Integration, the VLSI Journal
Computer arithmetic algorithms
Computer arithmetic algorithms
'Overturned-Stairs' Adder Trees and Multiplier Design
IEEE Transactions on Computers - Special issue on computer arithmetic
Computer arithmetic systems: algorithms, architecture and implementation
Computer arithmetic systems: algorithms, architecture and implementation
Fast multiplication: algorithms and implementation
Fast multiplication: algorithms and implementation
The complexity of simple computer architectures
The complexity of simple computer architectures
Hardware design
Computer Architecture: Complexity and Correctness
Computer Architecture: Complexity and Correctness
Introduction to VLSI Systems
A New Design Technique for Column Compression Multipliers
IEEE Transactions on Computers
Modified Booth Algorihtm for High Radix Multiplication
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
167 MHz Radix-4 Floating Point Multiplier
ARITH '95 Proceedings of the 12th Symposium on Computer Arithmetic
Reducing the number of counters needed for integer multiplication
ARITH '95 Proceedings of the 12th Symposium on Computer Arithmetic
STOC '79 Proceedings of the eleventh annual ACM symposium on Theory of computing
Multipliers and Datapaths
Performance/Area Tradeoffs in Booth Multipliers
Performance/Area Tradeoffs in Booth Multipliers
Technology Scaling Effects on Multipliers
Technology Scaling Effects on Multipliers
Computational Aspects of VLSI
Secondary Radix Recodings for Higher Radix Multipliers
IEEE Transactions on Computers
A parametric error analysis of Goldschmidt's division algorithm
Journal of Computer and System Sciences
Partial product reduction by using look-up tables for M×N multiplier
Integration, the VLSI Journal
Hi-index | 0.00 |
Booth Recoding is a commonly used technique to recode one of the operands in binary multiplication. In this way the implementation of a multipliers' adder tree can be improved in both cost and delay. The improvement due to Booth Recoding is said to be due to improvements in the layout of the adder tree especially regarding the lengths of wire connections and thus cannot be analyzed with a simple gate model. Although conventional VLSI models consider wires in layouts, they usually neglect wires when modeling the delay. To make the layout improvements due to Booth recoding tractable in a technology-independent way, we introduce a VLSI model that also considers wire delays and constant factors. Based on this model we consider the layouts of binary multipliers in a parametric analysis providing answers to the question whether to use Booth Recoding or not.We formalize and prove the folklore theorems that Booth recoding improves the cost and cycle time of 'standard' multipliers by certain constant factors. We also analyze the number of full adders in certain 4/2 trees