Integration, the VLSI Journal
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Booth encoding is a method of reducing the number of summands required to produce the multiplication result. This paper compares the performance/area tradeoffs for the different Booth algorithms when trees are used as the summation network. This paper shows that the simple non-Booth algorithm is not an efficient design, and that for small feature sizes the performance for the different Booth encoding schemes are comparable in terms of delay. The report also quantifies the effects of wires on the multiplier. As the feature size continues to decrease, wires will provide an ever increasing portion of the total delay. Booth 3 becomes more attractive since it is smaller.