Integration, the VLSI Journal
A novel 32-bit scalable multiplier architecture
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Modified booth truncated multipliers
Proceedings of the 14th ACM Great Lakes symposium on VLSI
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People traditionally have considered the number of counters in the critical path as the metric for the performance of a multiplier. This report presents the view that tree topologies which have the least number of levels do not always give the fastest possible multiplier when constrained to be part of a microprocessor. It proposes two new topologies: hybrid structure and higher order arrays which are faster than conventional tree topologies for typical datapaths.