Fault-Secure Parity Prediction Booth Multipliers
IEEE Design & Test
Integration, the VLSI Journal
New Self-Checking Booth Multipliers
International Journal of Applied Mathematics and Computer Science - Selected Problems of Computer Science and Control
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Booth encoding is a method of reducing the number of summands required to produce the multiplication result. This paper compares the performance/area tradeoffs for the different Booth algorithms when trees are used as the summation network. This paper shows that the simple non-Booth algorithm is not a viable design, and that currently Booth 2 is the best design. It also points out that in the future Booth 3 may offer the best performance/area ratio.