Self-checking and fault-tolerant digital design
Self-checking and fault-tolerant digital design
Design of fault-secure parity-prediction booth multipliers
Proceedings of the conference on Design, automation and test in Europe
Fault-Secure Parity Prediction Arithmetic Operators
IEEE Design & Test
Berger Check Prediction for Array Multipliers and Array Dividers
IEEE Transactions on Computers
Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
A self-checking ALU design with efficient codes
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
A New Code-Disjoint Sum-Bit Duplicated Carry Look-Ahead Adder for Parity Codes
ATS '01 Proceedings of the 10th Asian Test Symposium
Performance/Area Tradeoffs in Booth Multipliers
Performance/Area Tradeoffs in Booth Multipliers
A New Self-Checking Multiplier by Use of a Code-Disjoint Sum-Bit Duplicated Adder
ETS '04 Proceedings of the European Test Symposium, Ninth IEEE
New Self-checking Output-Duplicated Booth Multiplier with High Fault Coverage for Soft Errors
ATS '05 Proceedings of the 14th Asian Test Symposium on Asian Test Symposium
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This paper describes new technical challenges that arise from networking dynamical systems. In particular, the paper takes a look at the underlying phenomena and the resulting modeling problems that arise in such systems. Special emphasis is placed on ...