Design of fault-secure parity-prediction booth multipliers

  • Authors:

  • M. Nicolaidis;R. O. Duarte

  • Affiliations:

  • -;-

  • Venue:
  • Proceedings of the conference on Design, automation and test in Europe
  • Year:
  • 1998

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Abstract

The basic drawback of parity prediction arithmetic operators is that they may not be fault secure for single faults. In a recent work we have proposed a theory for achieving fault secure design for parity prediction multipliers and dividers. This paper has not considered the case of Booth multipliers using operand recoding. This case is analyzed here. Parity prediction logic and fault secure implementation for this scheme is derived.