Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Digital CMOS circuit design
Computer arithmetic algorithms
Computer arithmetic algorithms
On the effectiveness of residue code checking for parallel two's complement multipliers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Computer Arithmetic: Principles, Architecture and Design
Computer Arithmetic: Principles, Architecture and Design
Fault-Secure Parity Prediction Arithmetic Operators
IEEE Design & Test
Performance/Area Tradeoffs in Booth Multipliers
Performance/Area Tradeoffs in Booth Multipliers
An Operation-Centered Approach to Fault Detection in Symmetric Cryptography Ciphers
IEEE Transactions on Computers
Flexible multi-mode embedded floating-point unit for field programmable gate arrays
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Architecture Design for Soft Errors
Architecture Design for Soft Errors
Parameterized MAC unit generation for a scalable embedded DSP core
Microprocessors & Microsystems
Design of the coarse-grained reconfigurable architecture DART with on-line error detection
Microprocessors & Microsystems
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Parity-prediction arithmetic operator schemes are compatible with data paths and memory systems checked by parity codes. The drawback of these schemes is that they may not be fault secure for single faults, since they propagate to multiple output errors undetectable by the parity code. In a recent work we proposed a theory for achieving fault-secure design for parity-prediction multipliers and dividers. We did not consider the case of Booth multipliers using operand recoding. Since Booth multipliers are among the most popular, in this article we derive the parity-prediction logic for Booth multipliers and propose a fault-secure implementation for this scheme. Due to the particular structure of these multipliers, parity prediction is not as straightforward as in multipliers with non-recoded operands. Also, fault-secure design requires a specific solution to cope with even-cell fan-out signals.