TRAM: A Design Methodology for High-Performance, Easily Testable, Multimegabit RAMs
IEEE Transactions on Computers
A Recursive Carry-Lookahead/Carry-Select Hybrid Adder
IEEE Transactions on Computers
Minimizing energy dissipation in high-speed multipliers
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
An empirical study of on-chip parallelism
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Scalable Test Generators for High-Speed Datapath Circuits
Journal of Electronic Testing: Theory and Applications - Special issue on On-line testing
Software experience with concurrent C and LISP in a distributed system
CSC '88 Proceedings of the 1988 ACM sixteenth annual conference on Computer science
Digit-Serial Complex-Number Multipliers on FPGAs
Journal of VLSI Signal Processing Systems
Fault-Secure Parity Prediction Booth Multipliers
IEEE Design & Test
Accelerated Two-Level Carry-Skip Adders-A Type of Very Fast Adders
IEEE Transactions on Computers
Innovative Structures for CMOS Combinational Gates Synthesis
IEEE Transactions on Computers
On TSC Checkers for m-out-of-n Codes
IEEE Transactions on Computers
EUDOXUS: A WWW-based Generator of Reusable Arithmetic Cores
RSP '01 Proceedings of the 12th International Workshop on Rapid System Prototyping
A core generator for arithmetic cores and testing structures with a network interface
Journal of Systems Architecture: the EUROMICRO Journal
An 9-bit parallel pipelined multiplier based on the 3-bit recoding from booth's algorithm
SBCCI'99 Proceedings of the XIIth conference on Integrated circuits and systems design
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