The design and analysis of VLSI circuits
The design and analysis of VLSI circuits
Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Digital CMOS circuit design
Fault-tolerant computing: theory and techniques; Vol. 2
Fault-tolerant computing: theory and techniques; Vol. 2
Functional Testing of Semiconductor Random Access Memories
ACM Computing Surveys (CSUR)
Introduction to VLSI Systems
The chip complexity of binary arithmetic
STOC '80 Proceedings of the twelfth annual ACM symposium on Theory of computing
A complexity theory for VLSI
IEEE Transactions on Computers
LPRAM: a low power DRAM with testability
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
| Hi-index | 14.98 |
An architecture is proposed for multimegabit dynamic RAMs (random-access memories) that achieves higher testability and performance than the conventional four-quadrant RAMs. Applying the principle of divide and conquer, the RAM is partitioned into modules, each appearing as the leaf node of a binary interconnect network. Such a network carries the address/data/control bus, permitting the nodes to communicate among themselves as well as with the outside world. This architecture is shown to be easily testable. Parallelism in testing and partial self-test result in a large savings of testing time; the savings is independent of the test algorithm used. Unlike other testability schemes, this approach promises improved performance with only a small increase in chip area. It is also shown that the architecture is easily partionable and restructurable, with potential for yield and reliability improvement.