TRAM: A Design Methodology for High-Performance, Easily Testable, Multimegabit RAMs
IEEE Transactions on Computers
Parallel Testing for Pattern-Sensitive Faults in Semiconductor Random-Access Memories
IEEE Transactions on Computers
Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Introduction to VLSI Systems
An Algorithm to Test Rams for Physical Neighborhood Pattern Sensitive Faults
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
| Hi-index | 14.98 |
This paper modifies the tree RAM (TRAM) architecture[1] of multimegabit dynamic random access memories using a tree-star (TS) interconnection topology. The modified TS-RAM design offers a reduced access time and an improved yeild for the proposed TS-RAM architecture. We also propose an improved built-in self test (BIST) approach for the architecture.