The design and analysis of VLSI circuits
The design and analysis of VLSI circuits
Digital CMOS circuit design
A Way to Build Efficient Carry-Skip Adders
IEEE Transactions on Computers
Analysis and Design of CMOS Manchester Adders with Variable Carry-Skip
IEEE Transactions on Computers
A Spanning Tree Carry Lookahead Adder
IEEE Transactions on Computers - Special issue on computer arithmetic
Designing Optimum One-Level Carry-Skip Adders
IEEE Transactions on Computers
A Recursive Carry-Lookahead/Carry-Select Hybrid Adder
IEEE Transactions on Computers
A Recursive Carry-Lookahead/Carry-Select Hybrid Adder
IEEE Transactions on Computers
On Hardware for Computing Exponential and Trigonometric Functions
IEEE Transactions on Computers
Delay efficient 32-bit carry-skip adder
VLSI Design
| Hi-index | 14.99 |
This paper describes a new type of carry-skip adder, which can be faster than the conventional two-level carry-skip adders. A way to design optimum adders of this new type is described. In optimum adders of this type, the sizes of the sections of bit positions are bimodal, but the sizes of the blocks in each section are unimodal, unlike the bimodal block sizes in Guyot et al.'s traditional two-level carry-skip adders. A 60-b 2- mu m CMOS adder of this type is designed. This adder's simulated delay is approximately 12.6 ns.