An 9-bit parallel pipelined multiplier based on the 3-bit recoding from booth's algorithm

Authors:
Laércio Caldeira;Tales Cleber Pimenta;Evandro D. C. Cotrim
Affiliations:
Escola Federal de Engenharia de Itajubá;Escola Federal de Engenharia de Itajubá;Escola Federal de Engenharia de Itajubá
Venue:
SBCCI'99 Proceedings of the XIIth conference on Integrated circuits and systems design
Year:
1999

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Abstract

This paper presents the design of a 9-bit parallel multiplier based on the Booth's Algorithm using a 3-bit recoding. Although mentioned as "possible" in the literature, there are no references of its implementation. This multiplier offers a higher multiplication speed over the traditional implementation using only 2 bits, and offers a good speed/area ratio.