Digital CMOS circuit design
Performance analysis and design of a logic simulation machine
ISCA '87 Proceedings of the 14th annual international symposium on Computer architecture
Fundamentals of parallel logic simulation
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
A data-driven multiprocessor for switch-level simulation of vlsi circuits
A data-driven multiprocessor for switch-level simulation of vlsi circuits
A Hardware Architecture for Switch-Level Simulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Massively parallel switch-level simulation: a feasibility study
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Logic simulation on massively parallel architectures
ISCA '89 Proceedings of the 16th annual international symposium on Computer architecture
Breaking the barrier of parallel simulation of digital systems
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
An evaluation of the Chandy-Misra-Bryant algorithm for digital logic simulation
ACM Transactions on Modeling and Computer Simulation (TOMACS) - Special issue on parallel and distributed systems performance
Parallel logic simulation of VLSI systems
ACM Computing Surveys (CSUR)
Parallel logic level simulation of VLSI circuits
WSC '94 Proceedings of the 26th conference on Winter simulation
Parallel timing simulation on a distributed memory multiprocessor
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
A multidimensional study on the feasibility of parallel switch-level circuit simulation
Proceedings of the eleventh workshop on Parallel and distributed simulation
Potential performance of parallel conservative simulation of VLSI circuits and systems
ANSS '92 Proceedings of the 25th annual symposium on Simulation
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This paper presents a methodology for empirically determining the amount of parallelism on a CMOS VLSI chip. Six chips are measured, and the effect of input choice and circuit size is studied. The unexpectedly low parallelism measured here suggests that certain strategies for parallel simulators may be doomed, and earlier efforts to extrapolate parallelism from small circuits to large circuits may have been overly optimistic.