ACM Transactions on Programming Languages and Systems (TOPLAS)
Distributed discrete-event simulation
ACM Computing Surveys (CSUR)
SSIM: a software levelized compiled-code simulator
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Faster architectural simulation through parallelism
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Statistics for parallelism and abstraction level in digital simulation
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Characterization of parallelism and deadlocks in distributed digital logic simulation
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Reactive-process programming and distributed discrete-event simulation
Reactive-process programming and distributed discrete-event simulation
Techniques for unit-delay compiled simulation
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
LECSIM: a levelized event driven compiled logic simulation
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Breaking the barrier of parallel simulation of digital systems
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
An empirical study of on-chip parallelism
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Parallel logic simulation on general purpose machines
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
HERCULES—a system for high-level synthesis
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Fundamentals of parallel logic simulation
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Statistics on logic simulation
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Exploiting parallelism in a switch-level simulation machine
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
The directory-based cache coherence protocol for the DASH multiprocessor
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Asynchronous distributed simulation via a sequence of parallel computations
Communications of the ACM - Special issue on simulation modeling and statistical computing
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IEEE Design & Test
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ISCA '82 Proceedings of the 9th annual symposium on Computer Architecture
The Yorktown Simulation Engine: Introduction
DAC '82 Proceedings of the 19th Design Automation Conference
SIMULATION OF PACKET COMMUNICATION ARCHITECTURE COMPUTER SYSTEMS
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Parallel and distributed discrete event simulation: algorithms and applications
WSC '93 Proceedings of the 25th conference on Winter simulation
Support for Efficient Programming on the SB-PRAM
International Journal of Parallel Programming
SEAMS: simulation environment for VHDL-AMS
Proceedings of the 30th conference on Winter simulation
Efficient Execution of Time Warp Programs on Heterogeneous, NOW Platforms
IEEE Transactions on Parallel and Distributed Systems
PADS '00 Proceedings of the fourteenth workshop on Parallel and distributed simulation
Proceedings of the conference on Design, automation and test in Europe
Analysis and simulation of mixed-technology VLSI Systems
Journal of Parallel and Distributed Computing - Parallel and Distributed Discrete Event Simulation--An Emerging Technology
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Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Parallel Synchronization of Continuous Time Discrete Event Simulators
ICPP '97 Proceedings of the international Conference on Parallel Processing
Optimistic Synchronization of Mixed-Mode Simulators
IPPS '98 Proceedings of the 12th. International Parallel Processing Symposium on International Parallel Processing Symposium
Predicting the Performance of Synchronous Discrete Event Simulation
IEEE Transactions on Parallel and Distributed Systems
Distributed time, conservative parallel logic simulation on GPUs
Proceedings of the 47th Design Automation Conference
Massively Parallel Logic Simulation with GPUs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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We explore the suitability of the Chandy-Misra-Bryant (CMB) algorithm for the domain of digital logic simulation. Our evaluation is based on results for six realistic benchmark circuits, one of them being the R6000 microprocessor form MIPS. A quantitative evaluation of the concurrency exhibited by the CMB algorithm shows that an average of 42-196 element activations can be evaluated in parallel if arbitrarily many processors are available. One major factor limiting the parallel performance is the large number of deadlocks that occur. We present a classification of the types of deadlocks and describe them in terms of circuit structure. Using domain-specific knowledge, we propose and evaluate several methods for both reducing the number of deadlock occurences and for reducing the time spent on each occurence. Running on a 16-processor Encore Multimax we observe speedups of 6-9. While these self-relative speedups are larger than a parallel version of the traditional centralized-time event-driven algorithm, they come at the price of large overheads: significantly more complex element evaluations, extra element evaluations, and deadlock resolution time. These overheads overwhelm the advantages of using distributed time and consistently make the parallel performance of the CMB algorithm about three times slower than that of the traditional parallel event-driven algorithm. Our experience leads us to conclude that the distributed-time CMB algorithm does not present a viable alternative to the centralized-time event-driven algorithm in the domain of parallel digital logic simulation.