ACM Transactions on Programming Languages and Systems (TOPLAS)
Statistics on logic simulation
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Exploiting parallelism in a switch-level simulation machine
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Characterization of parallelism and deadlocks in distributed digital logic simulation
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Performance estimation in a massively parallel system
Proceedings of the 1990 ACM/IEEE conference on Supercomputing
Distributed and parallel demand driven logic simulation
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
An evaluation of the Chandy-Misra-Bryant algorithm for digital logic simulation
ACM Transactions on Modeling and Computer Simulation (TOMACS) - Special issue on parallel and distributed systems performance
Proceedings of the 1992 ACM/IEEE conference on Supercomputing
Parallel logic simulation of VLSI systems
ACM Computing Surveys (CSUR)
Distributed simulation for structural VHDL netlists
EURO-DAC '94 Proceedings of the conference on European design automation
Parallel logic simulation on general purpose machines
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
HERCULES—a system for high-level synthesis
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Analysis and simulation of mixed-technology VLSI Systems
Journal of Parallel and Distributed Computing - Parallel and Distributed Discrete Event Simulation--An Emerging Technology
Parallel Distributed-Time Logic Simulation
IEEE Design & Test
Performance Analysis of Synchronized Iterative Algorithms on Multiprocessor Systems
IEEE Transactions on Parallel and Distributed Systems
| Hi-index | 0.00 |
This paper presents statistics of several designs at four design abstraction levels - the instruction, behavioral, RTL, and gate levels. The data includes simulation time profiles, maximum speedup and limitations of parallelism, typical model evaluation times, event distributions, element intensities, and component counts for the four abstraction levels. This data is then used to analyze and evaluate several speed-up approaches: mixed-level simulation, parallel software simulators, parallel pipelined hardware accelerators, and decreased time resolution.The results show that element activity is around 0.1 to 0.5% at any particular time point. For the example circuits (3400 gates, 5000 gates, and 150,000 transistors), simulations show that parallelism can obtain speed-ups between 10-30. We found a factor of roughly ten speed-up between each of the abstraction levels.