Massively parallel switch-level simulation: a feasibility study

Authors:
S. A. Kravitz;R. E. Bryant;R. A. Rutenbar
Affiliations:
Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, Pennsylvania;Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, Pennsylvania;Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, Pennsylvania
Venue:
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Year:
1989

Citing 11
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Abstract

This work addresses the feasibility of mapping the COSMOS switch-level simulator onto a computer with thousands of simple processors. COSMOS preprocesses transistor networks into Boolean behavioral models, capturing the switch-level behavior of a circuit in a set of Boolean formulas. We describe a class of massively parallel computers and a mapping of COSMOS onto these computers. We discuss the factors affecting the performance of such a massively parallel simulator including: the amount of parallelism in the simulation model, performance measures for massively parallel machines, and the impact of event scheduling on simulator performance. We have developed compilation tools which automatically map a MOS circuit onto a massively parallel computer. Massively parallel switch-level simulation is illustrated by describing our pilot implementation on a 32k processor Thinking Machines Connection Machine System.