Circuit simulation on the connection machine

  • Authors:
  • D. M. Webber;A. Sangiovanni-Vincentelli

  • Affiliations:
  • University of California, Berkeley;University of California, Berkeley

  • Venue:
  • DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
  • Year:
  • 1987

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Abstract

Accurate circuit simulation is a very important step in the design of high performance integrated circuits. The ever increasing size of integrated circuits requires the use of an inordinate amount of computer time to be spent in circuit simulation. Parallel processors have been considered to speed up the simulation process. Massively parallel computers have been made available recently and present a new interesting paradigm for expensive CAD applications. This paper describes algorithms and programming techniques needed to develop SUM (Simulation Using Massively parallel computers), a relaxation-based circuit simulator on the Connection Machine, a massively parallel processor with up to 65536 processors. SUM can simulate circuits at almost constant CPU time per iteration, regardless of circuit size. SUM can simulate very large circuits. Circuit simulators running on the largest super computers can run circuits of comparable size, however SUM is easily scalable as the number of processors in the Connection Machine increases, with almost no increase in CPU time.