Parallel circuit simulation using hierarchical relaxation

Authors:
G. G. Hung;Y. C. Wen;K. Gallivan;R. Saleh
Affiliations:
Center for Supercomputing Research and Development, University of Illinois, Urbana, IL;Center for Supercomputing Research and Development, University of Illinois, Urbana, IL;Center for Supercomputing Research and Development, University of Illinois, Urbana, IL;Center for Supercomputing Research and Development, University of Illinois, Urbana, IL
Venue:
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Year:
1991

Citing 2
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A multiprocessor implementation of relaxation-based electrical circuit simulation

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Abstract

This paper describes a class of parallel algorithms for circuit simulation based on hierarchical relaxation that has been implemented on the Cedar multiprocessor. The Cedar machine is a reconfigurable, general-purpose supercomputer that was designed and implemented at the University of Illinois. A hierarchical circuit simulation scheme was developed to exploit the hierarchical organization of Cedar. The new algorithm and a number of key issues, such as multilevel circuit partitioning, data partitioning, cluster algorithm selection, and cluster algorithm implementation are described in this paper. Performance results on a variety of different configurations of Cedar are also presented that illustrate the benefits of the hierarchical approach over the non-hierarchical approach.