The C programming language
Classification Categories and Historical Development of Circuit Switching Topologies
ACM Computing Surveys (CSUR)
The Waveform Relaxation Method for Time-Domain Analysis of Large Scale Integrated Circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Parallel circuit simulation using hierarchical relaxation
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Waveform-relaxation-based circuit simulation on the Victor V256 parallel processor
IBM Journal of Research and Development
Tutorial on parallel processing for design automation applications (tutorial session)
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
A workstation-mixed model circuit simulator
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
An empirical analysis of the performance of a multiprocessor-based circuit simulator
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Misleading energy and performance claims in sub/near threshold digital systems
Proceedings of the International Conference on Computer-Aided Design
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The electrical circuit simulation of large integrated circuits is very expensive. New relaxation-based algorithms promise to reduce this cost by exploiting the properties of large networks. However, this speed improvement is not sufficient for the cost-effective analysis of very large circuits. While array processors have helped inprove the performance of circuit simulators, further improvement can be achieved by the use of special-purpose multiprocessors. In this paper, the implementation of a relaxation-based circuit simulation algorithm, called Iterated Timing Analaysis, on a multi-processor is described. Initial results indicate that this approach has a great deal of potential for reducing the cost of circuit simulation.