High-Speed Booth Encoded Parallel Multiplier Design
IEEE Transactions on Computers - Special issue on computer arithmetic
A dual precision IEEE floating-point multiplier
Integration, the VLSI Journal
Fault-Secure Parity Prediction Booth Multipliers
IEEE Design & Test
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
On the design of high performance digital arithmetic units
On the design of high performance digital arithmetic units
A Quadruple Precision and Dual Double Precision Floating-Point Multiplier
DSD '03 Proceedings of the Euromicro Symposium on Digital Systems Design
Computer Organization and Design
Computer Organization and Design
Hard vs. Soft: The Central Question of Pre-Fabricated Silicon
ISMVL '04 Proceedings of the 34th International Symposium on Multiple-Valued Logic
Embedded floating-point units in FPGAs
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
Dual-Mode Quadruple Precision Floating-Point Adder
DSD '06 Proceedings of the 9th EUROMICRO Conference on Digital System Design
Virtual Embedded Blocks: A Methodology for Evaluating Embedded Elements in FPGAs
FCCM '06 Proceedings of the 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Reconfigurable custom floating-point instructions (abstract only)
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
Construction of dual mode components for reconfiguration aware high-level synthesis
Proceedings of the Conference on Design, Automation and Test in Europe
Reducing the cost of floating-point mantissa alignment and normalization in FPGAs
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
Optimizing floating point units in hybrid FPGAs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Performance of Field Programmable Gate Arrays (FPGAs) used for floating-point applications is poor due to the complexity of floating-point arithmetic. Implementing floating-point units on FPGAs consume a large amount of resources. This makes FPGAs less attractive for use in floating-point intensive applications. Therefore, there is a need for embedded floating-point units (FPUs) in FPGAs. However, if unutilized, embedded FPUs waste space on the FPGA die. To overcome this issue, we propose a flexible multi-mode embedded FPU for FPGAs that can be configured to perform a wide range of operations. The floating-point adder and multiplier in our embedded FPU can each be configured to perform one double-precision operation or two single-precision operations in parallel. To increase flexibility further, access to the large integer multiplier, adder and shifters in the FPU is provided. Benchmark circuits were implemented on both a standard Xilinx Virtex-II FPGA and on our FPGA with embedded FPU blocks. The results using our embedded FPUs showed a mean area improvement of 5.2 times and a mean delay improvement of 5.8 times for the double-precision benchmarks, and a mean area improvement of 4.4 times and a mean delay improvement of 4.2 times for the single-precision benchmarks.