A Quadruple Precision and Dual Double Precision Floating-Point Multiplier

Authors:
Ahmet Akkas;Michael J. Schulte
Affiliations:
-;-
Venue:
DSD '03 Proceedings of the Euromicro Symposium on Digital Systems Design
Year:
2003

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Abstract

Double precision floating-point arithmetic is inadequatefor many scientific computations. This paper presents thedesign of a quadruple precision floating-point multiplierthat also supports two parallel double precision multiplications.Since hardware support for quadruple precisionarithmetic is expensive, a new technique is presented thatrequires much less hardware than a fully parallel quadrupleprecision multiplier. With this implementation, quadrupleprecision multiplication has a latency of three cycles andtwo parallel double precision multiplications have a latencyof only two cycles. The design is pipelined so that two doubleprecision multiplications can be started every cycle ora quadruple precision multiplication can be started everyother cycle.