What do we need beyond IEEE arithmetic?
Computer arithmetic and self-validating numerical methods
Parallel reduced area multipliers
Journal of VLSI Signal Processing Systems - Special issue on application-specific array processors
A Comparison of Three Rounding Algorithms for IEEE Floating-Point Multiplication
IEEE Transactions on Computers - Special issue on computer arithmetic
The Journal of Supercomputing
Power4 System Design for High Reliability
IEEE Micro
Small Multiplier-Based Multiplication and Division Operators for Virtex-II Devices
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Itanium 2 Processor Microarchitecture
IEEE Micro
The S/390 G5 Floating Point Unit Supporting Hex and Binary Architectures
ARITH '99 Proceedings of the 14th IEEE Symposium on Computer Arithmetic
A Combined Interval and Floating Point Multiplier
GLS '98 Proceedings of the Great Lakes Symposium on VLSI '98
Algorithms for Quad-Double Precision Floating Point Arithmetic
ARITH '01 Proceedings of the 15th IEEE Symposium on Computer Arithmetic
1-GHz HAL SPARC64® Dual Floating Point Unit with RAS Features
ARITH '01 Proceedings of the 15th IEEE Symposium on Computer Arithmetic
Instruction set enhancements for reliable computations
Instruction set enhancements for reliable computations
A Quadruple Precision and Dual Double Precision Floating-Point Multiplier
DSD '03 Proceedings of the Euromicro Symposium on Digital Systems Design
Multi-functional floating-point MAF designs with dot product support
Microelectronics Journal
Dual-mode floating-point adder architectures
Journal of Systems Architecture: the EUROMICRO Journal
VLIW coprocessor for IEEE-754 quadruple-precision elementary functions
ACM Transactions on Architecture and Code Optimization (TACO)
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Although most modern processors have hardware support for double precision or double-extended precision floating-point multiplication, this support is inadequate for many scientific computations. This paper presents the architecture of a quadruple precision floating-point multiplier that also supports two parallel double precision multiplications. Since hard-ware support for quadruple precision arithmetic is expensive, a new technique is presented that requires much less hard-ware than a fully parallel quadruple precision multiplier. With this architecture, quadruple precision multiplication has a latency of three cycles and two parallel double precision multiplications have latencies of only two cycles. The multiplier is pipelined so that two double precision multiplications can begin every cycle or a quadruple precision multiplication can begin every other cycle. The technique used for the dual-mode quadruple precision multiplier is also applied to the design of a dual-mode double precision floating-point multiplier that performs a double precision multiplication or two single precision multiplications in parallel. Synthesis results show that the dual-mode double precision multiplier requires 43% less area than a conventional double precision multiplier. The correctness of all the multipliers presented in this paper is tested and verified through extensive simulation.